The present invention relates to analog-to-digital converters. In particular, the present invention is directed toward calibration of isolated analog-to-digital converters.
Measurement data collected by isolated analog-to-digital converters (ADCs) in multiple data channels may be related. Data from the isolated ADCs may be transmitted to a microcontroller or programmable logic device for centralized processing. The gain and offset of individual channels relative to one another is an issue which may require attention. Such applications are precise, cost-sensitive applications where providing each ADC with a precise reference is not an affordable solution.
ADCs are known to need isolation in applications subject to different voltage levels. The reference voltage of an ADC is not necessarily the same as the reference voltage which would be observed by an outside observer (e.g., relative to absolute ground). Moreover, the recording equipment processor used with an ADC may work with another power supply, and the various power supplies may be very different both in voltage levels and in power supply characteristics.
For example, in a power meter chip, used to measure power consumption (e.g., in a residential or business metering or measuring system) with one or three phases, there may be provided a ground line and a live line. The live line may have a potential, for example, 220 Volts from the neutral line. Thus, in order to make a measurement on the ground or neutral line and simultaneously make a measurement on the live line, the ADC front end must be able to accommodate vastly different voltage levels (i.e., the voltage reference to the live line, such as 220 Volts absolute, and a ground reference). The measurement device and the data processor may need to be isolated electrically from one another.
It is known in the art to use isolation capacitors as an isolation barrier in multi-link systems. A transformer or other isolation device may also be used to isolate the ADC from the microcontroller or programmable logic device. However, such isolation barriers may make it difficult to calibrate the ADC since the microcontroller or programmable logic device may have difficulty sending a precise voltage reference signal through the isolation barrier.
FIG. 1 is a block diagram of a measurement system 9 of the prior art. Such measurement systems may be used to measure various analog parameters in environments where voltage isolation is required. For example, in residential power metering, a measurement device (front end) may be measuring power at line voltage (e.g., 220 Volts) and some form of isolation may be required to protect the user and processor (back end) which may be at a much lower potential. Similarly, in medical systems, voltage isolation may be required as a fail-safe to prevent a patient from being electrocuted due to potential differences between various medical monitoring devices connected to a patient.
Referring to FIG. 1, measurement system 9 may include a digital signal processor (DSP) 11, link chip 12, capacitor C113, analog-to-digital converter (ADC) and link chip 15, and a sensor 16. Sensor 16 may comprise any one of a number of known analog sensors for measuring a particular parameter (e.g., temperature, pressure, voltage, amperage, power consumption, or the like).
Analog-to-digital converter (ADC) and link chip 15 may convert the analog output of sensor 16 to a digital value (typically a one-bit data stream) and outputs this data stream to a digital signal processor (DSP) 11 via link chip 12 and isolation capacitor 13. In addition to digital data values transmitted from analog-to-digital converter (ADC) and link chip 15 to digital signal processor (DSP) 11, other signals may need to be exchanged between the two chips.
For example, clock signals and control signals (including calibration signals or voltage levels) may be transmitted from digital signal processor (DSP) 11 to analog-to-digital converter (ADC) through link chip 15. In addition, digital signal processor (DSP) 11 may need to provide power supply voltage to analog-to-digital converter through link chip 15. In the prior art, additional signal lines may be required for such additional signals, increasing the complexity and cost of the device.
In many applications it may be necessary to isolate analog-to-digital converter (ADC) from link chip 15 and digital signal processor (DSP) 11 due to differences in voltage potential. An isolation capacitor 13 may be employed to isolate the voltage potential between analog-to-digital converter and link chip 15 and digital signal processor (DSP) 11.
FIG. 2 is a block diagram of another embodiment of a measurement system 19 of the prior art. Measurement system 19 includes a digital application specific integrated circuit (ASIC) or programmable logic device (PLD) 21 such as a digital signal processor and link chip, a resistor 22, capacitor 23, transformer 24, analog-to-digital converter (ADC) 25 and capacitor 26.
ASIC or PLD 21 may include a transmitter 27 and receiver 29 coupled to each other through switch 28. Data may be selectively transmitted and received over the connection between ASIC or PLD 21 and ADC 25. In addition, ASIC or PLD 21 may provide power to ADC 25 through this same link.
ADC 25 may include a diode 30 and a rectifier 31. Signals from secondary winding 33 of transformer 24 may be rectified by rectifier 31 and diode 30 to produce a voltage a capacitor 26 which in turn is the power supply for ADC 25.
As in the embodiment of FIG. 1, transmitter 27 may transmit to primary winding 32 of transformer 24 a square wave which may be partially blocked or distorted by capacitor 23 from transformer 24. ADC 25 may detect a pause during the tri-state operation and takes over the data link, sending data and status back to receiver 29. During this take-over period, however, voltage at power supply 26 may droop significantly if many bits are transmitted, and full logic levels may not re-establish themselves.
In addition, an isolated ADC may require an accurate low noise reference voltage from, for example, a microcontroller. If the ADC is rendered in CMOS, a superquality voltage reference may be required for the ADC to accurately measure analog values. CMOS circuitry may be more susceptible to drift due to temperature variations and the like, as well as initial accuracy of measurement.
Further, in order to perform an absolute accurate conversion with an isolated ADC, it may be necessary to send an accurate low noise reference voltage across the isolation barrier. If the ADC is rendered in CMOS, a superquality voltage reference may be required for the ADC to accurately measure analog values. CMOS circuitry may be more susceptible to drift due to temperature variations and the like, as well as initial accuracy of measurement. A better reference, therefore, may be implemented on the isolated side.
Moreover, in some applications, it may be necessary to provide multiple isolated ADCs with precisely matched gains for acquiring related signals such that conversion data are known to be exactly at the same scale. These may be ratiometric measurements between several isolated points. Prior art techniques may use separate chips for each ADC side to provide a reference signal. However, such a solution creates extra cost and increases complexity and size of the overall circuitry.
Related measurement data collected by isolated analog-to-digital converters in multiple channels may be transmitted to a microprocessor or programmable logic device for centralized processing, to eliminate selected gain and offset effects common to the different analog-to-digital converters in the different channels, eliminating the consequences of drift in the different channels.
In particular, a pair of precision resistors is provided to calibrate the different channels. The ADCs may be factory calibrated and the ratio between the two precision resistors stored within the ADCs. The ADCs may later self-calibrate by comparing their relative gains to the stored resistor ratio. Gain of one of the ADCs may be adjusted relative to the other in order to maintain a relative gain calibration. Although absolute gain is not calibrated (as the resistors are isolated) for particular applications, only relative gain between the ADCs is relevant. Thus, the present invention provides a cost-effective and simple solution to relative gain calibration between isolated ADCs.
The system employs first and second sensors for receiving respective first and second analog signals. The signals from the respective sensors may be converted with respective first and second analog-to-digital converters into counterpart digital signals. Corresponding first and second transformers couple the separate signal streams into a data processing system connected to the first and second transformers, whereby the transformers isolate the data processing systems from the respective analog-to-digital converters.
First and second analog-to-digital converters may be referenced to respective local grounds, which may be at very different potentials. In normal operation, the respective analog-to-digital converters may employ on-chip CMOS bandgap references. These references have relatively high temperature drift and time drift characteristics. Such references may be calibrated with precisely matched inputs from the first and second resistors.
The resistors may be manufactured on a common substrate which features good thermal conduction and electrical insulation characteristics. Chips comprising ADC may be provided with silicon thermal meters. The apparatus may then be subject to a two-temperature factory calibration. The ratio variation of the first and second resistors over temperature and time may be less than 100 ppm.
Since the first and second resistors carry substantially the same current the ADCs do not drawing much current from the first and second resistors, a pair of ratio matched voltages is established with the first and second resistors for the calibration of the CMOS bandgap references in the respective ADCs to the aforementioned desired accuracy level.